The present invention relates to a method of forming a viahole in steps of fabricating semiconductor devices.
The processing technique in steps of fabricating LSI chips has become increasingly strict with the tendency toward finer-geometries and high integration of semiconductor devices.
In recent years, pattern printing by lithography and pattern processing by dry etching have been required to be improved particularly in terms of dimensional accuracy and dimensional margin in a region near processing limit along with the increased integration.
The number of stepped portions formed in a device is increased linearly with the number of interconnection layers. This tends to lower the focal depth in the exposure step in lithography, and to form stringers on the stepped portions at the time of dry etching.
To solve the above problems caused by the increased stepped portions, a process of planarizing an interlayer insulating film and/or an interconnection layer has been developed. In particular, an attempt has been made to improve the focal depth in lithography by achieving a high surface flatness through global planarization.
If an interlayer insulating film is perfectly planarized, it becomes possible to make smaller the amount of over-etching in dry etching upon formation of interconnections, and to enhance reliability of interconnections associated with step coverage of a metal film.
One of these techniques is to planarize an interlayer insulating film by chemical-mechanical polishing.
The technique for planarizing an interlayer insulating film by chemical-mechanical polishing will be described below.
An interlayer insulating film has a multi-layer structure in which a layer having a high polishing rate (for example, BPSG (Borophosphosilicate Glass) layer) is held by layers having a low polishing rate (for example, NSG (Non-doped Silicate Glass) layers). The surface of the interlayer insulating film is planarized using the layer having a low polishing rate as a polishing stopper, to eliminated stepped portions formed by a gate electrode, an interconnection and the like. The technique makes smooth the distribution of polishing rate within a wafer using a difference in polishing rate between two kinds of silicon oxide (SiO.sub.2) layers, or enlarges a margin in terminal detection of polishing, so that the non-uniformity in polishing which is increased linearly with a wafer diameter can be avoided. Accordingly, such a technique becomes further important in the future.
However, in the case of planarizing an interlayer insulating film having a multi-layer structure of layers different in polishing rate by chemical-mechanical polishing and forming a contact hole or viahole (hereinafter, referred to "viahole") in the interlayer insulating film, there occur the following disadvantages:
(a) When a viahole formed in a planarized interlayer insulating film is subjected to light etching before being buried with a metal, the layers (different in polishing rate) of the interlayer insulating film in the viahole, particularly, on a side wall of the viahole are unevenly etched, and consequently, irregularities are formed on the side wall of the viahole. PA1 (b) When the viahole having such a shape is buried with a metal by sputtering, the interlayer insulating film tends to be stepwise cut at portions unevenly etched, leading to a failure in burying of the viahole.
On the other hand, when the viahole is buried with a tungsten plug, an adhesive layer is discontinuously formed on a side wall of the viahole, resulting in separation at the discontinuous portions.
Incidentally, before a viahole is buried with a metal, a native oxide film formed on a bottom portion of the viahole is removed by light etching. This is essential for achieving a stable and low resistance connection between the metal buried in the viahole and the underlying layer. The light etching is performed by dipping in a buffer hydrofluoric acid (solution having a composition of HF: 0.1 wt %, NH.sub.4 F: 39.9 wt %, and H.sub.2 O: 60.0 wt %) for 60 seconds. The amount to be etched is about 3.0 nm for a thermal oxide film.
When an interlayer insulating film having a multi-layer structure of layers different in polishing rate is subjected to light etching, the etching rate becomes high at interfaces between the different insulating layers of the interlayer insulating film, as shown in FIGS. 4A and 4B.
FIG. 4A shows a state in which an interlayer insulating film 112 is formed in such a manner as to cover a gate electrode 111 and is formed with a viahole 113. The interlayer insulating film 112 is composed of a NSG (Non-doped Silicate Glass) layer 114 having a thickness of 200 nm (containing an offset oxide film (thickness: 120 nm) formed on the gate electrode 111), and a PSG (Phosphosilicate Glass) layer 115 having a thickness of 200 nm formed on the upper surface of the NSG layer 114.
After that, a native oxide film 116 (shown by the two-dot chain line) formed on a bottom portion of the viahole 113 is removed by light etching using a buffer hydrofluoric acid for 60 seconds. At this time, the etching rate becomes very high in the vicinity of an interface between the insulating layers of the interlayer insulating film 112, so that a recessed portion 117 is formed at the interface portion on a side wall of the viahole 113.
FIG. 4B shows a state in which an interlayer insulating film 123 is formed in such a manner as to cover a diffusion layer 122 formed in a semiconductor substrate 121 and is formed with a viahole 124. The interlayer insulating film 123 is composed of a NSG layer 125 having a thickness of 200 nm, a BPSG (Borophosphosilicate Glass) layer 126 having a thickness of 210 nm, an NSG layer 127 having a thickness of 50 nm, and a PSG layer 128 having a thickness of 200 nm. Also in this case, similarly, when a native oxide film 129 (shown by the two-dot chain line) formed on a bottom portion of the viahole 124 is removed by light etching, the etching rate becomes very high in the vicinity of an interface between the insulating layers of the interlayer insulating film 123. Consequently, recessed portions 129 and 129 are formed at the interface portions on the side wall of the viahole 124. Furthermore, the NSG layer 127 lower than the BPSG layer 126 and the PSG layer in a polishing rate 128 remains in an overhang shape in the viahole 124.
A process for improving such a shape of a side wall of a viahole is required for fabrication of the future devices having finer-geometries.